As the feature size of transistors in large scale integrated circuits becomes smaller continuously, a conventional gate arrangement of silicon dioxide/poly silicon is being replaced with a high dielectric constant (High-K) gate dielectric/Metal gate arrangement gradually. To meet the multi-threshold requirement for devices, a dual-metal-gate design is typically utilized. In other words, metallic materials with different work functions are used for an NMOSFET and a PMOSFET, so that effective work functions of their metal gates approximate the conduction band edge (˜4.2 eV) and the valence band edge (˜5.1 eV) of a silicon substrate, respectively.
It is desired to adjust an effective work function of a metal gate more efficiently. Especially in the gate-last process, there are problems, such as, filling of the high-K gate dielectric/metal gate arrangement and limited options for metal gate materials. It is important but difficult in the high-K dielectric/Metal gate engineering to adjust the effective work function of the metal gate.